For the past few months I was looking everywhere to find some resources to learn Verilog while also building projects. After a lot of time spent online, I was able to find some really good resources that would help you understand it by also helping you build projects alongside.

You would require any pre-requisites for the following courses, but you'll be able to understand them fairly well considering they're some excellent resources.

First one are the Onur Mutlu Lectures on Digital Design and Computer Architecture. This will help build the concept that'll be applied in your codes.

The second one is Digital Circuit Design using Verilog lectures by Anas Salah Eddin. His lectures are very detailed and simple to understand. He also builds several projects such as FIFO and UART by the end of the playlist.

The final resource I would suggest is the popular DDCA Book by Harris and Harris (whichever edition you'd prefer, MIPS, ARM, RISC-V)

It isn't mandatory for you to follow these resources in order, but I'd suggest you to cover either the book or Onur Mutlu's Lectures before jumping on to Verilog lectures, or at least build a proper conceptual base, since that would help you to follow through those Verilog lectures.

Though the lectures follow with Verilog, the book provides SystemVerilog examples and exercises. They aren't much different from one another. Once you've understood Verilog, there's barely much to do for SV.

I hope someone who needs these resources finally finds them, just like I was looking for them a few months ago.

Hi, Almost dead Computer Engineering redditors.
I have a Computer Systems Architecture Course and I want to implement a 3 state Kalman Filter in Vivado. I'll get Real time data from Gy-87 (MPU-6050), through Esp-32 into my pc. Now the problem is idk how to get it into Vivado without an FPGA. I'm a sopho in uni with this being our first technical CE course. Any help is appreciated.
And where do i learn system verilog properly?

i am starting my career in vlsi ...
can anyone suggest a clear cut roadmap for me any best resources , how to utilise them and make my work easier
i would love to connect and learn

Has anyone ever written a custom FPGA SPI master state machine to completely initialize the AD9361 by doing register level writes? I want to get in contact with somebody who has done before this hardware level control of AD9361.

Have any of you worked on this project before? Could you share it for reference? Also, what optimization does it offer compared to CMOS?

I am taking a VLSI course and have a final project coming up; I would like to choose a topic related to card decoding—specifically focusing on the decoder itself. I would appreciate any advice or insights from those with experience in this area

I am 2nd year and I want to start verilog. Can someone please provide me for the best resources available on internet?

This sounds so stupid, guys. I am sorry, I know. I just really feel like I need to learn this because I want to. I want to learn a useful new skill that will put me ahead. I want it to be something I am genuinely interested in, because I am very, very interested. I am 15 and can tell you how to assemble a system, fix it, and diagnose it. I have a base-level understanding of how the parts work. So the problem is: I never coded, ever. I could not tell you jack squat.

But I have had this giant surge in my brain telling me to do this and learn something nice, so here I am. I have no good basis to come off of.

Hell, I didn't even know how to do the first lesson in HDLbits. I really am starting with no experience. I am hoping you guys can wish me some luck that I will learn this before senior year.

Because I know nothing about even the basics for this language, I am hoping I can find some cool sites to help me learn this.

I have tried NandGame and still didn't understand it, so I am hoping I could get some useful sites to learn the basics so I can start writing the language within a 5-month basis casually. Sorry to disturb. Thanks

hello, can anyone suggest good projects related to Logics Circuit and Design? tya for help🫶

In 2020 I built a FIR band-pass filter for a university course: designed the response in MATLAB, generated the Verilog with Filter Design HDL Coder, ran the generated testbench, zero errors, submitted, put it on GitHub. It got forked 8 times.

Last week I read it properly for the first time since. The 51-tap design doesn't filter anything. Its output is the sign of the accumulator and nothing else.

The cause was two boxes on the "Specify Precision" tab. I'd set the output to s8,32 – 8 bits, 32 fractional bits, i.e. a range of ±2.98e-8 – fed from an s20,20 accumulator with a range of ±0.5. That's 2^24 times narrower than the thing feeding it. The generated conversion saturates for literally every non-zero value:

assign output_typeconvert =
        (sum50[19] == 1'b0 & sum50[18:0] != 19'b0) ? 8'b01111111 :
        (sum50[19] == 1'b1 && sum50[18:0] != 19'b1111111111111111111) ? 8'b10000000 :
        $signed({sum50[19], 7'b0000000});

Sweep the whole accumulator range through that and you get exactly two values: -128 and +127.

The part that actually bothers me is the testbench. It's 7,000 generated lines, 3,429 stimulus samples, a checker, an error counter. I counted the distinct values in its expected-output array:

8'h80 (-128):  1765
8'h7f (+127):  1607
8'h00 (0):       57

That's the entire golden reference. MATLAB generated the vectors from the same fixed-point spec that produced the RTL, so the model and the implementation agreed perfectly – they were wrong in exactly the same way. A generated testbench is a self-consistency check, not a correctness check. If the spec is wrong, the golden data encodes the mistake with perfect fidelity and reports zero errors.

The 11-tap serial design in the same repo had a quieter bug: accumulator s26,24 (range ±2) with wrap-on-overflow, but sum|h| = 2.375. A full-scale sine at the centre frequency clears it by 1.4% so it looks fine. A square wave at the same frequency wraps on 191 of 400 samples, and because it wraps rather than saturates the sample comes back sign-inverted:

FAIL sample 12: filter_out = 1744840192, expected -2550127104

Fixes were one word length each (output = the accumulator; accumulator gets one more bit). The real fix was replacing the stored-vector bench with one that checks against an independent reference model – impulse response must equal the coefficients, output must match a 64-bit integer model under square/random/worst-case-sign stimulus – plus a three-line check that the output takes more than 3 distinct values. Both benches fail on the 2020 RTL and pass on the fixed one.

Full write-up with the plots and the before/after RTL:

https://abdullahansarii.medium.com/my-fir-bandpass-filter-passed-its-own-testbench-for-six-years-it-was-a-sign-detector-7bc1fecfa2df

Repo (make sim runs everything under Icarus in a few seconds):

https://github.com/AbdullahAnsarii/BandPassFilter

If you've got generated HDL sitting next to a generated testbench that passes: check sum|h| against your accumulator range, and count the distinct values on your output. Took me six years.

Hi everyone 🙂

I often see beginners asking where to start with Verilog or how to get more practice, so I wanted to share an update on FPGAPourTous (french for "FPGAForAll").

Alongside the existing VHDL courses and exercises, I’ve added Verilog courses and a growing collection of practical exercises.

There are currently 134 Verilog exercises across beginner, intermediate and advanced levels:

✅ Schematic to Verilog: study a hardware diagram, implement the corresponding module and test it with Icarus Verilog.
✅ Specification to RTL: build a module from its requirements and validate it with a self-checking testbench.
✅ Verilog to schematic: read RTL code and identify the hardware it describes.

Topics range from encoders and FSMs to arbitration, SRAM controllers, DMA and cache logic.

There’s currently less Verilog content than VHDL content, but I’ll keep adding courses and exercises over time (I'm working on it during my free time, after work). The idea is to give you more ways to practise, whichever language you use.

Everything is available in English and French. Feedback and suggestions are welcome!

👉 https://fpgapourtous.fr/en/exercises?language=verilog&utm_source=reddit&utm_medium=organic_social&utm_campaign=reddit_organic_2026&utm_content=post_verilog_exercises

Hello everyone,
I am starting my journey into VLSI engineering and want to master Verilog (HDL) from the absolute basics up to advanced application-level concepts.

My goal is to build strong foundational knowledge so I can eventually transition into front-end RTL design/verification. My Background:

• 3rd-year Electronics undergraduate student
• My current knowledge of digital logic is basic gates only Suggest a best book to learn Verilog completely